X86 Accumulation Adequate Approach
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14 June 11:38
This page is traveling to altercate the differences amid absolute approach and adequate approach operations in the x86 processors. This page will aswell altercate how to access adequate mode, and how to avenue adequate mode. Avant-garde Operating Systems (Windows, Unix, Linux, BSD, etc...) all accomplish in adequate mode, so alotof accumulation accent programmers wont charge this information. However, this advice will be decidedly advantageous to humans who are aggravating to program kernels or bootloaders.
When an x86 processor is powered up or reset, it is in absolute mode. In absolute mode, the x86 processor about acts like a actual fast 8086. Alone the abject apprenticeship set of the processor can be used. Absolute approach anamnesis abode amplitude is bound to 1MiB of addressable memory, and anniversary anamnesis articulation is bound to 64KiB. Absolute Approach is provided about to accommodate backwards-compatability with 8086 and 80186 programs.
In adequate approach operation, the x86 can abode 4GiB of abode space. This may map anon assimilate the concrete RAM (in which case, if there is beneath than 4GiB of RAM, some abode amplitude is unused), or paging may be acclimated to arbitrarily construe amid basic addresses and concrete addresses.
In Adequate mode, the segments in anamnesis can be assigned protection, and attempts to breach this aegis couldcause a Accepted Aegis exception.
Protected mode, amidst additional things, is controlled by the Ascendancy Registers, which are labelled CR0, CR2, CR3, and CR4.
Long approach was alien by AMD with the appearance of the Athlon64 processor. Continued approach allows the chip to admission 64-bit anamnesis space, and admission 64-bit continued registers. Some 16 and 32-bit instructions do not plan (or plan correctly) in Continued Mode. x86-64 processors in Absolute approach act absolutely the like 16 bit chips, and x86-64 chips in adequate approach act absolutely like 32-bit processors. To alleviate the 64-bit capabilities of the chip, the dent haveto be switched into Continued Mode.
The everyman 5 $.25 of the ascendancy annals CR0 accommodate 5 flags that actuate how the arrangement is traveling to function. This cachet annals has 1 banderole that we are decidedly absorbed in: the Adequate Approach Accredit banderole (PE). Actuality are the accepted accomplish to entering adequate mode:
#Create a Accurate GDT (Global Descriptor Table)
#Create a 6 byte pseudo-descriptor to point to the GDT
#Disable Interrupts (set the Arrest Accredit banderole in the FLAGS annals to 0).
#Set the PE bit of the MSW or CR0 register
#Jump abreast (e.g. to the afterward instruction, e.g. jmp $+2)
#Load data articulation registers with accurate selector(s) to anticipate GP exceptions if the registers are used
#Load CS and EIP with a accurate abode to alpha active cipher (Far jump)
#Enable Interrupts.
Following capacity will allocution added about these steps.
To access Continued Approach on an x86, 64-bit processor (x86-64), the software first needs to access adequate mode, and then set the adapted flags for Continued Mode.
The CR registers may alone be accessed in adequate mode. For this reason, paging and task-switching can alone be performed by the processor if in adequate mode.
The CR0 Annals has 6 $.25 that are of absorption to us. The low 5 $.25 of the CR0 register, and the accomplished bit. Actuality is a representation of CR0:
CR0: |PG|----RESERVED----|ET|TS|EM|MP|PE|
We admit the PE banderole as getting the banderole that puts the arrangement into adequate mode.
;PG: The PG banderole turns on anamnesis paging. We will allocution added about that in a second.
;MP: The Adviser Coprocessor flag. This banderole controls the operation of the Delay instruction.
;ET: The Addendum Blazon Flag. ET (also alleged R) tells us which blazon of coprocessor is installed. If ET = 0, an 80287 is installed. if ET = 1, an 80387 is installed.
;EM: The Challenge Flag. If this banderole is set, coprocessor instructions will accomplish an exception.
;TS: The Assignment Switched flag. This banderole gets set automatically if the processor switches to a new task.
CR2 contains a amount alleged the Page Accountability Beeline Abode (PFLA). If a page accountability occurs, the abode accessed is stored in CR2.
The high 20 $.25 of CR3 are alleged the Page Agenda Abject Annals (PDBR). The PDBR holds the concrete abode of the page directory.
CR4 contains several flags authoritative avant-garde appearance of the processor.
Paging is a appropriate job that the chip will perform, in adjustment to create the accessible bulk of anamnesis in a arrangement arise beyond then it infact is, and be added activating then it infact is. In a paging system, a assertive bulk of amplitude is laid abreast on the harddrive (or on any accessory storage) alleged the paging book (or bandy partition). The concrete RAM, accumulated with this paging book are alleged the basic anamnesis of the system.
The absolute basic anamnesis is torn down into chunks or pages of memory, anniversary usually getting 4096 bytes (although this amount can be altered on altered systems). These pages can then be confused about throughout the basic memory, and all pointers central those pages will be automatically adapted to point to the new locations by referencing them to a all-around paging directory, that the chip maintains. The arrow to the accepted paging agenda is stored in the CR3 register.
pages that arent in common use may be confused to the paging book on the harddisk drive, to chargeless up amplitude in the concrete RAM for pages that charge to be accessed added frequently, or that crave faster access. Account and autograph pages to the harddrive is a apathetic operation, and common paging may access the ache on the disk, so in some systems with earlier drives, it may be a acceptable anticipation to about-face the paging capabilities of the processor off. This is able by toggleing the PG banderole in the CR0 register.
A page accountability occurs if the arrangement attempts to apprehend from a page that is apparent as not present in the paging directory/table, if the arrangement attempts to address data above the boundaries of a currently accessible page, or if any amount of additional errors action in the paging system. If a page accountability occurs, the accessed anamnesis abode is stored in the CR2 register.
In accession to real, protected, and continued modes, there are additional modes that x86 processors can enter, for altered uses. :
;Virtual Mode:This approach is provided for backwards compatability, so that 8086 software can run on added avant-garde processors.
;System Administration Mode:This approach enables the processor to accomplish arrangement tasks after arresting the operating arrangement or additional software.
;Big Absolute Mode:This is like absolute mode, except that it enables admission to the absolute 4Gb of addressable anamnesis in 32-bit processors.
This page is traveling to altercate the differences amid absolute approach and adequate approach operations in the x86 processors. This page will aswell altercate how to access adequate mode, and how to avenue adequate mode. Avant-garde Operating Systems (Windows, Unix, Linux, BSD, etc...) all accomplish in adequate mode, so alotof accumulation accent programmers wont charge this information. However, this advice will be decidedly advantageous to humans who are aggravating to program kernels or bootloaders.
When an x86 processor is powered up or reset, it is in absolute mode. In absolute mode, the x86 processor about acts like a actual fast 8086. Alone the abject apprenticeship set of the processor can be used. Absolute approach anamnesis abode amplitude is bound to 1MiB of addressable memory, and anniversary anamnesis articulation is bound to 64KiB. Absolute Approach is provided about to accommodate backwards-compatability with 8086 and 80186 programs.
In adequate approach operation, the x86 can abode 4GiB of abode space. This may map anon assimilate the concrete RAM (in which case, if there is beneath than 4GiB of RAM, some abode amplitude is unused), or paging may be acclimated to arbitrarily construe amid basic addresses and concrete addresses.
In Adequate mode, the segments in anamnesis can be assigned protection, and attempts to breach this aegis couldcause a Accepted Aegis exception.
Protected mode, amidst additional things, is controlled by the Ascendancy Registers, which are labelled CR0, CR2, CR3, and CR4.
Long approach was alien by AMD with the appearance of the Athlon64 processor. Continued approach allows the chip to admission 64-bit anamnesis space, and admission 64-bit continued registers. Some 16 and 32-bit instructions do not plan (or plan correctly) in Continued Mode. x86-64 processors in Absolute approach act absolutely the like 16 bit chips, and x86-64 chips in adequate approach act absolutely like 32-bit processors. To alleviate the 64-bit capabilities of the chip, the dent haveto be switched into Continued Mode.
The everyman 5 $.25 of the ascendancy annals CR0 accommodate 5 flags that actuate how the arrangement is traveling to function. This cachet annals has 1 banderole that we are decidedly absorbed in: the Adequate Approach Accredit banderole (PE). Actuality are the accepted accomplish to entering adequate mode:
#Create a Accurate GDT (Global Descriptor Table)
#Create a 6 byte pseudo-descriptor to point to the GDT
#Disable Interrupts (set the Arrest Accredit banderole in the FLAGS annals to 0).
#Set the PE bit of the MSW or CR0 register
#Jump abreast (e.g. to the afterward instruction, e.g. jmp $+2)
#Load data articulation registers with accurate selector(s) to anticipate GP exceptions if the registers are used
#Load CS and EIP with a accurate abode to alpha active cipher (Far jump)
#Enable Interrupts.
Following capacity will allocution added about these steps.
To access Continued Approach on an x86, 64-bit processor (x86-64), the software first needs to access adequate mode, and then set the adapted flags for Continued Mode.
The CR registers may alone be accessed in adequate mode. For this reason, paging and task-switching can alone be performed by the processor if in adequate mode.
The CR0 Annals has 6 $.25 that are of absorption to us. The low 5 $.25 of the CR0 register, and the accomplished bit. Actuality is a representation of CR0:
CR0: |PG|----RESERVED----|ET|TS|EM|MP|PE|
We admit the PE banderole as getting the banderole that puts the arrangement into adequate mode.
;PG: The PG banderole turns on anamnesis paging. We will allocution added about that in a second.
;MP: The Adviser Coprocessor flag. This banderole controls the operation of the Delay instruction.
;ET: The Addendum Blazon Flag. ET (also alleged R) tells us which blazon of coprocessor is installed. If ET = 0, an 80287 is installed. if ET = 1, an 80387 is installed.
;EM: The Challenge Flag. If this banderole is set, coprocessor instructions will accomplish an exception.
;TS: The Assignment Switched flag. This banderole gets set automatically if the processor switches to a new task.
CR2 contains a amount alleged the Page Accountability Beeline Abode (PFLA). If a page accountability occurs, the abode accessed is stored in CR2.
The high 20 $.25 of CR3 are alleged the Page Agenda Abject Annals (PDBR). The PDBR holds the concrete abode of the page directory.
CR4 contains several flags authoritative avant-garde appearance of the processor.
Paging is a appropriate job that the chip will perform, in adjustment to create the accessible bulk of anamnesis in a arrangement arise beyond then it infact is, and be added activating then it infact is. In a paging system, a assertive bulk of amplitude is laid abreast on the harddrive (or on any accessory storage) alleged the paging book (or bandy partition). The concrete RAM, accumulated with this paging book are alleged the basic anamnesis of the system.
The absolute basic anamnesis is torn down into chunks or pages of memory, anniversary usually getting 4096 bytes (although this amount can be altered on altered systems). These pages can then be confused about throughout the basic memory, and all pointers central those pages will be automatically adapted to point to the new locations by referencing them to a all-around paging directory, that the chip maintains. The arrow to the accepted paging agenda is stored in the CR3 register.
pages that arent in common use may be confused to the paging book on the harddisk drive, to chargeless up amplitude in the concrete RAM for pages that charge to be accessed added frequently, or that crave faster access. Account and autograph pages to the harddrive is a apathetic operation, and common paging may access the ache on the disk, so in some systems with earlier drives, it may be a acceptable anticipation to about-face the paging capabilities of the processor off. This is able by toggleing the PG banderole in the CR0 register.
A page accountability occurs if the arrangement attempts to apprehend from a page that is apparent as not present in the paging directory/table, if the arrangement attempts to address data above the boundaries of a currently accessible page, or if any amount of additional errors action in the paging system. If a page accountability occurs, the accessed anamnesis abode is stored in the CR2 register.
In accession to real, protected, and continued modes, there are additional modes that x86 processors can enter, for altered uses. :
;Virtual Mode:This approach is provided for backwards compatability, so that 8086 software can run on added avant-garde processors.
;System Administration Mode:This approach enables the processor to accomplish arrangement tasks after arresting the operating arrangement or additional software.
;Big Absolute Mode:This is like absolute mode, except that it enables admission to the absolute 4Gb of addressable anamnesis in 32-bit processors.
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